Schmidt trigger circuits are the circuits for performing waveform shaping so that a signal that changes in an analog manner can be handled as a digital signal, and are used for preventing occurrence of chattering at a voltage in the vicinity of a threshold voltage thereof, thereby supplying a stable output signal to other circuit. An example of the Schmidt trigger circuits described above is described in Patent Document 1. The Schmidt trigger circuit described in Patent Document 1 includes two inverters having different thresholds, of which input terminals are connected in common, a logic circuit for inverting or noninverting the output signals of these inverters, and a latch circuit for obtaining output signals with levels thereof changed according to the logic output signals of this logic circuit.
FIG. 4 is a circuit diagram showing a configuration of a conventional Schmidt trigger circuit. The Schmidt trigger circuit in FIG. 4 is the circuit comparable to the Schmidt trigger circuit described in Patent Document 1. A driver circuit 103 for performing output from a Schmidt trigger circuit 100 to other circuit is further added. The Schmidt trigger circuit 100 in FIG. 4 includes a Vp/Vn setting unit 101 and an RS latch circuit 102. An input terminal IN for inputting a signal from outside is connected to inputs of inverters INV11 and INV12 in the Vp/Vn setting unit 101. The Vp/Vn setting unit 101 is constituted from the inverter INV11 for determining a positive trigger voltage level Vp, the inverter INV12 for determining a negative trigger voltage level Vn, and an inverter INV13 for inverting the output signal of the inverter INV12. Outputs of the inverters INV11 and INV13 are connected to inputs of the RS latch unit 102 in a subsequent stage, respectively. The RS latch unit 102 is constituted from NAND gates NAND11 and NAND12 of which one inputs are cross-coupled to outputs of the NAND gates NAND12 and NAND11, respectively. The other input of the NAND gate NAND11 that is not cross-coupled is connected to the output of the inverter INV11, and the other input of the NAND gate NAND12 that is not cross-coupled is connected to the output of the inverter INV13. The output of the NAND gate NAND11 is connected to the driver unit 103 in a subsequent stage. In the driver unit 103, an inverter INV14 and INV15 are connected in series. The driver unit 103 buffers and transmits a signal output from the NAND gate NAND11 to an output terminal OUT within an integrated circuit.
The positive trigger voltage Vp is the input threshold level of the inverter INV11, while the negative trigger voltage Vn is the input threshold level of the inverter INV12. Between both of the voltage levels, there is a relationship of Vp>Vn, so that a level difference (Vp−Vn) corresponds to a so-called hysteresis width.
Next, operations of units when a signal S101 applied to the input terminal IN rises slowly will be described. First, when the signal S101 at the input terminal IN exceeds the Vn level, the inverter INV12 is inverted, and the inverter INV13 is inverted next. The level of a signal S102 thereby transitions from a low level (L) to a high level (H). Then, when the signal S101 exceeds the Vp level, the inverter INV11 is inverted. A signal S103 thereby transitions from the H to the L.
A signal S104 from the RS latch unit 102 has been fixed in an L state, and a signal S105 has been fixed in an H state, before that. The logic level of the signal S104 is the negative (inverted) logical product of the logic level of the signal S103 and the logic level of the signal S105. Thus, the transition of the signal S103 from the H to the L causes transition of the signal S104 from the L to the H. On the other hand, the logic level of the signal S105 is the negative logical product of the logic level of the signal S102 and the logic level of the signal S104. Thus, the transition of the signal S104 from the L to the H causes transition of the signal S105 from the to H the L. When the state of the signal S104 is noted, though the level of the signal S101 temporarily falls down and the signal S103 returns from the L to the H, the level of the signal S104 does not change because the signal S105 is at the L. This state is referred to as being “latched”. This state is maintained unless the level of the signal S101 becomes the Vn or less and the signal S102 is then inverted.
A signal S106 of the output terminal OUT outputs (drives) the level of the signal S104 without alteration. As seen from the side of the output terminal, once the level of the signal S101 at the input terminal rises from the low level to become the positive trigger voltage Vp or higher, the signal S106 at the output terminal OUT is inverted from the L to the H. Thereafter, until the level of the signal S101 has become the negative trigger voltage Vn or lower, the signal S106 will not be inverted from the H to the L. With the operations as described above, even when the signal S101 at the input terminal IN has slowly risen, occurrence of chattering in the output signal can be prevented.
The above description is directed to the operations when the signal S101 at the input terminal IN has slowly risen. Conversely, even when the signal S101 has slowly fallen, the H/L levels of the respective units transition almost in reverse. Thus, once the level of the signal S101 has become the negative trigger voltage Vn or less, the signal S106 of the output terminal OUT is inverted from the H to the L. Thereafter, until the level of the signal S101 has become the positive trigger voltage Vp or higher, the signal S106 of the output OUT is not inverted from the L to the H.
Patent Document 2 discloses a Schmidt trigger circuit of an inverter type.
[Patent Document 1]
JP Patent Kokai Publication No. JP-A-2-105715 (FIG. 1)
[Patent Document 2]
JP Patent Kokai Publication No. JP-A-10-163826 (FIG. 5)